In the traditional MOS transistor process, polysilicon is commonly used as the gate material, but with continuous reduction in the device geometry, a higher gate leakage current is caused due to reduction in the thickness of the polysilicon gate/gate oxidation layer. The feature size of the existing device enters 32 nm node, at this scale, a solution of substituting the high-K dielectrics/metal gate (HKMG) structure for the gate oxidation layer/polysilicon gate structure has been put forward. It is reported by Intel that the gate leakage current may be reduced to one tenth of what it has been when high-K dielectric materials are used. So far, application of high-K dielectrics/metal gate structure becomes an inexorable trend for the development of the integrated circuit of generation of techniques of 32 nm and below.
However, in terms of the process of manufacturing a transistor of HKMG structure, two camps, which are the school of gate-first process represented by IBM and the school of gate-last process represented by Intel, respectively, exist within the industry. The gate-first integration scheme is similar to the existing polysilicon gate/gate oxidation layer process, but the metal gate is vulnerable to multiple thermal processing including high temperature junction annealing, thereby causing drift of electrical properties. In the gate-last integration, the polysilicon gate will be substituted by the metal gate subsequently through the following thermal processing and relevant processes. The gate-last process has an advantage that all processes within the metal silicide working procedure will not have an effect on the high-K insulating material or metal gate. For now, the gate-last integration scheme is a unique HKMG technology that is applied to product.
The existing method for manufacturing a CMOS device of HKMG structure by using a gate-last process is that, when the HKMG structures of an NMOS and a PMOS are manufactured and the contact holes are etched as shown in FIG. 1, since the depth to width ratio d/w of the contact hole of source/drain S/D is gradually increased with continuous reduction in the width w of the contact hole, from 32 nm node, the complicated process including two photolithographes and two etchings is forced to be used. Meanwhile, deposition of interconnection metal in such contact holes also becomes difficult. This will inevitably lead to a great increase in the manufacturing cost. Furthermore, as shown in the FIGURE, another disadvantage is that, while performing metal deposition to the source/drain contact hole, the deposited metal (typically W or Cu) may easily enter into the device per se to destroy the performance of the device since the contact hole is straightly down to the thinner metal silicide layer on the source/drain.